Viktor Puš

Publikace

• 2020

  KEKELY Lukáš, CABAL Jakub, PUŠ Viktor a KOŘENEK Jan. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. In: Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: IEEE Computer Society, 2020, s. 49-56. ISBN 978-1-7281-9535-3.
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• 2018

  CABAL Jakub, BENÁČEK Pavel, KEKELY Lukáš, KEKELY Michal, PUŠ Viktor a KOŘENEK Jan. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018, s. 249-258. ISBN 978-1-4503-5614-5.
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  KUČERA Jan, KEKELY Lukáš, PUŠ Viktor, PIECEK Adam a KOŘENEK Jan. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, s. 177-178. ISBN 978-1-4503-5902-3.
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• 2016

  MATOUŠEK Denis, KOŘENEK Jan a PUŠ Viktor. High-speed Regular Expression Matching with Pipelined Automata. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, s. 93-100. ISBN 978-1-5090-5602-6.
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• 2015

  KEKELY Lukáš, KUČERA Jan, PUŠ Viktor, KOŘENEK Jan a VASILAKOS Athanasios. Software Defined Monitoring of Application Protocols. IEEE Transactions on Computers, roč. 65, č. 2, 2015, s. 615-626. ISSN 0018-9340.
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• 2014

  ZÁVODNÍK Tomáš, KEKELY Lukáš a PUŠ Viktor. CRC based hashing in FPGA using DSP blocks. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, s. 179-182. ISBN 978-1-4799-4558-0.
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  PUŠ Viktor, KEKELY Lukáš a KOŘENEK Jan. Design Methodology of Configurable High Performance Packet Parser for FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, s. 189-194. ISBN 978-1-4799-4558-0.
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  KEKELY Lukáš, PUŠ Viktor a KOŘENEK Jan. Software Defined Monitoring of Application Protocols. In: Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014, s. 1725-1733. ISBN 978-1-4799-3360-0.
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  KEKELY Lukáš, PUŠ Viktor, BENÁČEK Pavel a KOŘENEK Jan. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014, s. 264-267. ISBN 978-3-00-044645-0.
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• 2012

  KEKELY Lukáš, PUŠ Viktor a KOŘENEK Jan. Low-Latency Modular Packet Header Parser for FPGA. In: ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012, s. 77-78. ISBN 978-1-4503-1685-9.
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  KAŠTIL Jan, KOŘENEK Jan, KOŠAŘ Vlastimil, PUŠ Viktor a TOBOLA Jiří. Netbench: Framework for Evaluation of Packet Processing Algorithms. Brno: Fakulta informačních technologií VUT v Brně, 2012.
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  PUŠ Viktor a KOŘENEK Jan. Reducing memory in high-speed packet classification. In: Proceedings of the 8th International Wireless Communications and Mobile Computing Conference. Limassol: Frederick University, 2012, s. 437-442. ISBN 978-1-4577-1377-4.
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• 2011

  PUŠ Viktor, KAJAN Michal a KOŘENEK Jan. Hardware Architecture for Packet Classification with Prefix Coloring. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, s. 231-236. ISBN 978-1-4244-9753-9.
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  PUŠ Viktor, TOBOLA Jiří, KAŠTIL Jan, KOŠAŘ Vlastimil a KOŘENEK Jan. Netbench - the Framework for Evaluation of Packet Processing Algorithms. In: Proceedings of the 7th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. New York: IEEE Computer Society, 2011, s. 95-96. ISBN 978-0-7695-4521-9.
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  PUŠ Viktor. Packet Classification Algorithms. In: Počítačové architektury a diagnostika. Stará Lesná: Fakulta elektrotechniky a informatiky Slovenskej technickej univerzity v Bratislave, 2011, s. 157-162. ISBN 978-80-227-3552-0.
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• 2010

  KOŘENEK Jan a PUŠ Viktor. Memory Optimization for Packet Classification Algorithms in FPGA. In: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň: IEEE Computer Society, 2010, s. 297-300. ISBN 978-1-4244-6610-8.
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  PUŠ Viktor. Optimizations of packet classification algorithms. In: Počítačové architektury & diagnostika 2010. Češkovice: Fakulta informačních technologií VUT v Brně, 2010, s. 153-158. ISBN 978-80-214-4140-8.
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• 2009

  PUŠ Viktor. Algoritmy pro klasifikaci paketů. In: Počítačové architektury a diagnostika 2009. Zlín: Univerzita Tomáše Bati ve Zlíně, 2009, s. 130-135. ISBN 978-80-7318-847-4.
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  PUŠ Viktor a KOŘENEK Jan. Fast and scalable packet classification using perfect hash functions. In: Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays. Association for Computing Machinery. New York: Association for Computing Machinery, 2009, s. 229-236. ISBN 978-1-60558-410-2.
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  KOŘENEK Jan a PUŠ Viktor. Memory Optimization for Packet Classification Algorithms. In: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Association for Computing Machinery. New York: Association for Computing Machinery, 2009, s. 165-166. ISBN 978-1-60558-630-4.
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• 2008

  PUŠ Viktor. Fast Packet Classification Algorithm in Hardware. In: Junior Scientist Conference 2008. Vídeň, 2008, s. 65-66. ISBN 978-3-200-01612-5.
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  PUŠ Viktor. Fast Packet Classification Using Perfect Hash Functions. In: ACM Student Research Competition 2008. Praha, 2008, s. 9-16. ISBN 978-80-01-04205-2.
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  PUŠ Viktor. Rychlá klasifikace paketů s využitím perfektních hashovacích funkcí. In: Proceedings EEICT 2008. Brno, 2008, s. 236-238. ISBN 978-80-214-3615-2.
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