Project Details

Paralelní architektury a programování pro CBSE - vývoj kursu

Project Period: 1. 1. 1998 - 31. 12. 1998

Project Type: grant

Code: IMG-97-CZ-2065

Agency: European Commision - Tempus Phare

Program:

English title
Parallel Architectures and Programming for CBSE - course development
Type
grant
Team members
Dvořák Václav, Prof. Ing., DrSc. (UIVT FEI VUT) , research leader
Publications

1998

  • DVOŘÁK Václav and SLLAME Azeddien M. An FPGA-Based Systolic Serial Multiplier. In: Proceedings of the 5th Electronic Devices and Systems Conference 1998. Brno: unknown, 1998, pp. 394-397. ISBN 80-214-1198-8. Detail
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