Faculty of Information Technology, BUT

Publication Details

Design Methodology of Configurable High Performance Packet Parser for FPGA

PUŠ Viktor, KEKELY Lukáš and KOŘENEK Jan. Design Methodology of Configurable High Performance Packet Parser for FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 189-194. ISBN 978-1-4799-4558-0.
Czech title
Metodologie návrhu konfigurovatelného a vysoko výkonného analyzátoru paketů pro FPGA
Type
conference paper
Language
english
Authors
Puš Viktor, Ing., Ph.D. (CESNET)
Kekely Lukáš, Ing., Ph.D. (DCSY FIT BUT)
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)
Keywords
Packet Parsing, Latency, FPGA
Abstract
Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.
Published
2014
Pages
189-194
Proceedings
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014, Warsaw, PL
ISBN
978-1-4799-4558-0
Publisher
IEEE Computer Society
Place
Warszawa, PL
DOI
BibTeX
@INPROCEEDINGS{FITPUB10616,
   author = "Viktor Pu\v{s} and Luk\'{a}\v{s} Kekely and Jan Ko\v{r}enek",
   title = "Design Methodology of Configurable High Performance Packet Parser for FPGA",
   pages = "189--194",
   booktitle = "17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2014,
   location = "Warszawa, PL",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4799-4558-0",
   doi = "10.1109/DDECS.2014.6868788",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10616"
}
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