Publication Details

Acceleration of DSP algorithms using FPGAs

DULÍK Tomáš. Akcelerace DSP algoritmů v hradlových polích FPGA. In: Sborník prací studentů a doktorandů. Brno: Faculty of Electrical Engineering and Computer Science BUT, 1998, pp. 39-40.

Type

conference paper

Language

english

Authors

Dulík Tomáš, Ing. (DCSE FEECS BUT)

Keywords

DSP, DTMF, XILINX, FPGA, Digital Signal Processor

Annotation

This work shows possibilities of acceleration of the DSP algorithms in Xilinxs' FPGAs, digital signal processors and in Pentium (MMX). Using the example of DTMF decoder algorithm, it shows working design of a DSP unit in Xilinx FPGA and compares the results with the same decoder, running on TMS320C32 signal processor.

Published

1998

Pages

39-40

Proceedings

Sborník prací studentů a doktorandů

Volume

Publisher

Faculty of Electrical Engineering and Computer Science BUT

Place

Brno, CZ

BibTeX

@INPROCEEDINGS{FITPUB5628,
   author = "Tom\'{a}\v{s} Dul\'{i}k",
   title = "Acceleration of DSP algorithms using FPGAs",
   pages = "39--40",
   booktitle = "Sborn\'{i}k prac\'{i} student\r{u} a doktorand\r{u}",
   volume = 4,
   year = 1998,
   location = "Brno, CZ",
   publisher = "Faculty of Electrical Engineering and Computer Science BUT",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/5628"
}