Publication Details

The use of VHDL in designing with gate arrays

ZENDULKA Jaroslav. The use of VHDL in designing with gate arrays. In: Proceedings of MOSIS'96, Volume 2. Krnov, 1996, pp. 142-147. ISBN 80-85988-03-8.

Type

conference paper

Language

english

Authors

Zendulka Jaroslav, Doc. Ing., CSc. (DCSE FEECS BUT)

Keywords

field programmable gate array, Xilinx, VHDL, simulation

Annotation

The paper describes design tools for WorkView and XACT development systems that are used for designs with field programmable gate arrays by Xilinx. The tools make possible to use VHDL description as an alternative design entry which enables to simulate designs with so called X-BLOX modules directly. First a typical design flow supported by the XACT development system is explained and motivation for an alternative design entry discussed. Then an approach for the development of models of Xilinx X-BLOX modules in VHDL that was used in a library called X_PACK is described.

Published

1996

Pages

142-147

Proceedings

Proceedings of MOSIS'96, Volume 2

ISBN

80-85988-03-8

Place

Krnov, CZ

BibTeX

@INPROCEEDINGS{FITPUB6651,
   author = "Jaroslav Zendulka",
   title = "The use of VHDL in designing with gate arrays",
   pages = "142--147",
   booktitle = "Proceedings of MOSIS'96, Volume 2",
   year = 1996,
   location = "Krnov, CZ",
   ISBN = "80-85988-03-8",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6651"
}