Detail publikace

The use of VHDL in designing with gate arrays

ZENDULKA Jaroslav. The use of VHDL in designing with gate arrays. In: Proceedings of MOSIS'96, Volume 2. Krnov: MARQ, 1996, s. 142-147. ISBN 80-85988-03-8.

Typ

článek ve sborníku konference

Jazyk

angličtina

Autoři

Zendulka Jaroslav, Doc. Ing., CSc. (UIVT FEI VUT)

Rok

1996

Strany

142-147

Sborník

Proceedings of MOSIS'96, Volume 2

ISBN

80-85988-03-8

Vydavatel

MARQ

Místo

Krnov, CZ

BibTeX

@INPROCEEDINGS{FITPUB6651,
   author = "Jaroslav Zendulka",
   title = "The use of VHDL in designing with gate arrays",
   pages = "142--147",
   booktitle = "Proceedings of MOSIS'96, Volume 2",
   year = 1996,
   location = "Krnov, CZ",
   ISBN = "80-85988-03-8",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/6651"
}