Publication Details

Methodology of RTL circuit testability analysis

PEČENKA Tomáš. Methodology of RTL circuit testability analysis. In: Proceedings of 9th conference and competition STUDENT EEICT 2003. Brno: Brno University of Technology, 2003, pp. 243-245. ISBN 80-214-2377-3.

Czech title

Metody analýzy testovatelnosti na úrovni RT

Type

conference paper

Language

english

Authors

Pečenka Tomáš, Ing. (DCSY FIT BUT)

URL

http://www.fit.vutbr.cz/~pecenka/pubs/2003_eeict.pdf PDF

Keywords

testability, DFT, RT level, full scan, partial scan, testable kernel

Abstract

During early design stages design for testability (DFT) issues must be dealt with. Various methods exist which can be used to support testability of the circuit. These methods can work on different levels of circuit description. This work deals with methods of scan type that operate with circuit on the register transfer level (RT). An attention is paid to the utilization of testable kernels to reduce test application time.

Published

2003

Pages

243-245

Proceedings

Proceedings of 9th conference and competition STUDENT EEICT 2003

Conference

ELECTRICAL ENGINEERING, INFORMATION AND COMMUNICATION TECHNOLOGIES 2003, Brno, CZ

ISBN

80-214-2377-3

Publisher

Brno University of Technology

Place

Brno, CZ

BibTeX

@INPROCEEDINGS{FITPUB7391,
   author = "Tom\'{a}\v{s} Pe\v{c}enka",
   title = "Methodology of RTL circuit testability analysis",
   pages = "243--245",
   booktitle = "Proceedings of 9th conference and competition STUDENT EEICT 2003",
   year = 2003,
   location = "Brno, CZ",
   publisher = "Brno University of Technology",
   ISBN = "80-214-2377-3",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7391"
}