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Metodika identifikace testovatelných bloků v obvodu na úrovni RT

HERRMAN Tomáš. Metodika identifikace testovatelných bloků v obvodu na úrovni RT. In: Počítačové architektury a diagnostika 2007. Plzeň: University of West Bohemia in Pilsen, 2007, pp. 67-76. ISBN 978-80-7043-605-9.
English title
Methodology for Identification Testable Blocks in Circuit on RT Level
Type
conference paper
Language
czech
Authors
Keywords
Testable Block, formal model, testability, scan method, evolutionary algorithm, RT level
Abstract
The concept of Testable block developed on formal model on RT level is presented in the paper. Principles of identification of Testable block are defined. In the next part the details of implementation of methodology is described. At the end of paper is stated contend of doctoral thesis.
Published
2007
Pages
67-76
Proceedings
Počítačové architektury a diagnostika 2007
Conference
Počítačové architektury a diagnostika 2007, Srní, CZ
ISBN
978-80-7043-605-9
Publisher
University of West Bohemia in Pilsen
Place
Plzeň, CZ
BibTeX
@INPROCEEDINGS{FITPUB8453,
   author = "Tom\'{a}\v{s} Herrman",
   title = "Metodika identifikace testovateln\'{y}ch blok\r{u} v obvodu na \'{u}rovni RT",
   pages = "67--76",
   booktitle = "Po\v{c}\'{i}ta\v{c}ov\'{e} architektury a diagnostika 2007",
   year = 2007,
   location = "Plze\v{n}, CZ",
   publisher = "University of West Bohemia in Pilsen",
   ISBN = "978-80-7043-605-9",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/8453"
}
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