Faculty of Information Technology, BUT

Publication Details

The Design of On-line Checkers and Their Use in Verification and Testing

KOTÁSEK Zdeněk and STRAKA Martin. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, vol. 2009, no. 3, pp. 8-15. ISSN 1335-8243.
Czech title
The Design of On-line Checkers and Their Use in Verification and Testing
Type
journal article
Language
english
Authors
Keywords
on-line checker, on-line testing, verification, communication protocol, PSL, FoCs, ModelSim, FPGA
Abstract
In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. The results and compare of both methodologies are described. The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.
Published
2009
Pages
8-15
Journal
Acta Electrotechnica et Informatica, vol. 2009, no. 3, ISSN 1335-8243
BibTeX
@ARTICLE{FITPUB9009,
   author = "Zden\v{e}k Kot\'{a}sek and Martin Straka",
   title = "The Design of On-line Checkers and Their Use in Verification and Testing",
   pages = "8--15",
   journal = "Acta Electrotechnica et Informatica",
   volume = 2009,
   number = 3,
   year = 2009,
   ISSN = "1335-8243",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9009"
}
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