Faculty of Information Technology, BUT

Publication Details

Fault Tolerant System Design and SEU Injection Based Testing

STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk and MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems, vol. 2013, no. 37, pp. 155-173. ISSN 0141-9331.
Czech title
Návrh systémů odolných proti poruchám a testování pomocí SEU injekce
Type
journal article
Language
english
Authors
Keywords

fault tolerant system, FPGA, partial reconfiguration, controller, on-line checker, duplex, TMR, SEU, simulation, framework, fault injection

Abstract

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

Annotation

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

Published
2013
Pages
155-173
Journal
Microprocessors and Microsystems, vol. 2013, no. 37, ISSN 0141-9331
Book
Microprocessors and Microsystems Journal SI: Digital System Safety and Security
Publisher
Elsevier Science
BibTeX
@ARTICLE{FITPUB9902,
   author = "Martin Straka and Jan Ka\v{s}til and Zden\v{e}k Kot\'{a}sek and Luk\'{a}\v{s} Mi\v{c}ulka",
   title = "Fault Tolerant System Design and SEU Injection Based Testing",
   pages = "155--173",
   booktitle = "Microprocessors and Microsystems Journal SI: Digital System Safety and Security",
   journal = "Microprocessors and Microsystems",
   volume = 2013,
   number = 37,
   year = 2013,
   ISSN = "0141-9331",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9902"
}
Files
Back to top