Exploring the Limits of Vertical Reuse Automation in PSS-Driven SoC Verification

As System-on-Chip (SoC) designs integrate increasingly diverse and software-driven components, verification reuse becomes critical for managing complexity across block, subsystem, and system levels. Despite advances in automation, the theoretical and practical boundaries of vertical reuse in complex SoC integrations remain underexplored. This paper investigates the limits of vertical reuse in Portable Stimulus Standard (PSS) workflows by applying a static analysis-based toolchain to a real-world SoC design. In PSS, reusable verification intent is captured as Portable Models (PMs), which combine abstract scenario definitions with realization-layer bindings to design interfaces. While prior work demonstrated that static analysis enables vertical reuse on designs of various sizes and complexities, this study examines how far such reuse can be extended as integration progresses toward full SoC levels. Using a Keccak-based cryptographic accelerator integrated through two distinct architectures - loosely coupled and tightly coupled - the feasibility of vertical reuse across six integration contexts is evaluated. The results show that static connectivity analysis supports reuse across hierarchy levels but that SoC-level reuse increasingly intersects with software-driven control, requiring additional modeling effort. This case study highlights both the reach and the limits of structural automation in enabling PM reuse, providing insight into when automation suffices and where additional modeling effort is required.