Faculty of Information Technology, BUT

Course details

Functional Verification of Digital Systems

FVS Acad. year 2015/2016 Summer semester 5 credits

Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping.

Guarantor

Language of instruction

Czech

Completion

Examination (written+oral)

Time span

26 hrs lectures, 8 hrs laboratories, 18 hrs projects

Assessment points

60 exam, 20 labs, 20 projects

Department

Lecturer

Instructor

Subject specific learning outcomes and competences

A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.

Learning objectives

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.

Prerequisite kwnowledge and skills

Digital system design, basic programming skills.

Study literature

Lecture notes in e-format.

Fundamental literature

  • Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
  • Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217
  • Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
  • Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
  • Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.

Syllabus of lectures

  1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
  2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
  3. Introduction to functional verification. Functional verification techniques.
  4. Verification methodologies. HVL languages.
  5. Pseudo-random stimuli generation, direct tests, constraints.
  6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
  7. Self-checking mechanisms.
  8. Assertions. Assertion languages. Errors reporting.
  9. Assertion-based verification.
  10. Emulation and prototyping.
  11. Hardware debugging.
  12. Industry lecture.
  13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

Syllabus - others, projects and individual work of students

Design and implementation of verification environment for a selected digital systém.

Progress assessment

Labs and project in due dates.

Exam prerequisites

Requirements for class accreditation are not defined.

Course inclusion in study plans

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