Faculty of Information Technology, BUT

Course details

Processor Architecture

ACH Acad. year 2017/2018 Winter semester 5 credits

The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on SIMD streaming instructions and on graphical processors (SIMT). Parallelization of numerical calculations for GPU is also covered (CUDA). Techniques of  low-power processors are also explained.

Guarantor

Language of instruction

Czech

Completion

Credit+Examination (written)

Time span

26 hrs lectures, 10 hrs pc labs, 16 hrs projects

Assessment points

60 exam, 10 half-term test, 5 labs, 25 projects

Department

Lecturer

Instructor

Subject specific learning outcomes and competences

Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. Get acquainted with processor performance measurement. The knowledge of architecture and hardware support of parallel computation on graphic processors can be directly applied for acceleration of intensive calculations. 

Learning objectives

To familiarize students with architecture of the newest processors exploiting the instruction-level, thread-level and data-level parallelism. To clarify the role of a compiler and its cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical processors and its use for acceleration of numerical calculations (GPGPU), and with low-power techniques in processors for mobile applications.  

Prerequisite kwnowledge and skills

Von Neumann computer architecture, memory hierarchy, programming in assembly language, compiler's tasks and functions

Study literature

Fundamental literature

  • Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1
  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 493 s., ISBN: 978-0-12-383872-8
  • Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
  • Jeffers, J., and Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 2013, Morgan Kaufmann, p. 432), ISBN: 978-0-124-10414-3

Syllabus of lectures

  1. Scalar processors. Pipelined instruction processing and compiler asistance
  2. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  3. Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
  4. Optimization of instruction and data fetching. Examples of superscalar CPUs.
  5. Multi-threaded processors.
  6. Data parallelism. SIMD extensions and vectorization.
  7. Architecture of graphics processing units, SIMT programming model.
  8. CUDA programming language, thread and memory model.
  9. Synchronisation and reduction on GPU, design and tuning of GPU codes.
  10. Stream processing, multi-GPU systems, GPU libraries.
  11. Architecture of many core systems (MIC, Xeon Phi) and their programming.
  12. VLIW processors. SW pipelining, predication, binary translation.
  13. Low power processors.

Syllabus - others, projects and individual work of students

  • Performance evaluation and code optimization using OpenMP 4.0
  • Acceleration of computational job using CUDA 8.0 

 

Progress assessment

Assessment of two projects, 13 hours in total and, computer laboratories and a midterm examination.

Controlled instruction

  • Missed labs can be substituted in alternative dates (monday or friday)
  • There will be a place for missed labs in the last week of the semester.

Exam prerequisites

To get 20 out of 40 points for projects and midterm examination.

Course inclusion in study plans

  • Programme IT-MSC-2, field MBI, MIN, MIS, MMM, MSK, any year of study, Elective
  • Programme IT-MSC-2, field MBS, MMI, any year of study, Compulsory-Elective group C
  • Programme IT-MSC-2, field MGM, 2nd year of study, Elective
  • Programme IT-MSC-2, field MPV, 2nd year of study, Compulsory
  • Programme IT-MSC-2, field MSK, 2nd year of study, Compulsory-Elective group C
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