Faculty of Information Technology, BUT

Course details

Digital Systems Design (in English)

INCe Acad. year 2018/2019 Winter semester 5 credits

Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic. Boolean algebra, logic functions and their representations: logic expressions, reduction methods, design of combinational logic networks. Analysis of logic networks behaviour: signal races, hazards. Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit. Sequential logic networks, latches and flip-flops. State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider. Design of simple digital equipment: design CAD tools, description tools, design strategy. Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL. Simple asynchronous networks: design, analysis of behaviour, hazards.

Guarantor

Language of instruction

English

Completion

Examination (written)

Time span

39 hrs lectures, 13 hrs exercises

Assessment points

60 exam, 40 half-term test

Department

Lecturer

Instructor

News


* This course is prepared for incoming Erasmus+ students only, and it is instructed in English.
* This course will be open if a certain/sure minimum of enrolled students is at least five students.

2018-05-18: An expected timetable for fall/winter semester.
2018-09-10: The first meeting will be on Wed-09-19 at 9:00 h in the seminar room L314.

* Stop and Check Test will be held on Wed 2018-10-24, 9:00 h a.m., in seminar room L314.
* Mid-Term Test will be held on Wed 2018-11-21, 9:00 h a.m., in seminar room L314.
* Regular Exam (ReEx) will be held on Wed 2018-12-05, 9:00 h a.m., in seminar room L314.
* 1st Correction Exam (1stCor) will be held on Fri 2019-01-04, 9:00 h a.m., in room L314.
* On Wed 2019-01-09, 10:00 h a.m., in room L314, the 1stCor Exam solutions demonstration will be held, and answers to students questions too. Present students will propose a day of the 2nd Correctin Exam (2ndCor) if interested.
* 2nd Correction Exam (2ndCor) will be held on Tue 2019-01-15, 9:30 h a.m., in room L314.

Subject specific learning outcomes and competences

A practical use of selected methods for specification of combinational and sequential logic networks. An encompassment of analysis and design of simple combinational and sequential networks. An encompassment of analysis and design of simple digital equipments using combinational and sequential circuits and blocks.

Learning objectives

To obtain an overview and fundamental knowledge of a practical use of selected methods for description of combinational and sequential logic networks which are inside digital equipments. To learn how to analyze and design combinational logic devices. To learn how to analyze and design sequential logic devices. To learn about design of digital circuits consisting of combinational and sequential logic devices.

Prerequisite kwnowledge and skills

The sets, relations and mappings. Basic terms and axioms of Boolean algebra. The elementary notions of the graph theory. Rudiments of electrical engineering phenomena and basic active and passive electronic elements.

Study literature

  • Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
  • Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  • McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  • Cheung, J.Y. - Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  • Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
  • Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
  • Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
  • Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  • Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  • Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  • Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). Student-Text of the FIT, Brno UT, 2003 (WWW version).
  • Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). Student-Text of the FIT, Brno UT, 2003.
  • Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). Student-Text of the FIT Brno UT, FIT Brno UT, 2003 (WWW version).

Fundamental literature

  • McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
  • Cheung, J.Y., Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
  • Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
  • Katz, R.H.: Contemporary Logic Design. Addison-Wesley/Benjamin-Cummings Publishing CO, Redwood City, CA, USA, ISBN 0-8053-2703-7, 1993.
  • Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.

Syllabus of lectures

  • Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
  • Boolean algebra, logic functions and their representations, logic expressions.
  • Reduction methods: Qiune-McCluskey tabular method, Petrick's cover function.
  • Reduction methods: Karnaugh maps, logic and functional diagrams.
  • Analysis of logic networks behaviour: signal races, hazards.
  • Selected logic modules: adder, subtractor, multiplexer, demultiplexer, decoder, coder, comparator, arithmetic and logic unit.
  • Sequential logic networks, latches and flip-flops.
  • State machines and their representations. Design of synchronized sequential networks: state assigment, optimization and implementation. Register, counter, shift register, impulse divider.
  • Integrated circuits families: SSI, MSI, LSI. Programmable logic devices: gate arrays, PROM, PLA, PAL.
  • Simple asynchronous networks: design, analysis of behaviour, hazards.

Syllabus of numerical exercises

  • Binary digit system: positional notation, conversion of base, binary codes, binary arithmetic.
  • Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
  • Logic expressions. Qiune-McCluskey tabular reduction method, Petrick's cover function.
  • Reduction methods: Karnaugh maps, logic and functional diagrams.
  • Logic functions implementation using SSI i.cs. Behaviour analysis of logic networks: signal races, hazards.
  • Selected logic modules: adders, subtractor.
  • State machines and their representations. Design of synchronized sequential networks.
  • Design of logic networks based on MSI and LSI i.cs. Programmable logic devices: gate arrays, PROM, PLA, PAL.

Progress assessment

  • Stop and Check Test: 20 points.
  • Mid-Semester Exam: 20 points.
  • Final Exam: 60 points.
    Passing bounary for ECTS assessment: 50 points.

Controlled instruction

Test, mid-term exam and final exam are the monitored, and points earning, education. Test and mid-term exam are without correction eventuality. Final exam has two additional correction eventualities.

Exam prerequisites

Requirements for class accreditation are not defined.

Schedule

DayTypeWeeksRoomStartEndLect.grpGroupsInfo
Tueexam2019-01-15 L314 09:0011:50 INTE 2nd Correction
Wedlecturelectures L314 09:0011:50 INTE
Wedexercise2019-01-09 L314 10:0011:50 INTE 1StCor: Solutions
Friexam2019-01-04 L314 09:0011:50 INTE 1st Correction
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