Course details

# Digital Systems Design

INC Acad. year 2019/2020 Summer semester 5 credits

Guarantor

Deputy Guarantor

Language of instruction

Completion

Time span

Assessment points

Department

Lecturer

Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)

Martínek Tomáš, Ing., Ph.D. (DCSY FIT BUT)

Instructor

Subject specific learning outcomes and competences

Learning objectives

Why is the course taught

Prerequisite kwnowledge and skills

Study literature

- Maurer, P.M.: Logic Design. University of South Florida, WWW Edition.
- Bout, D.V.: Pragmatic Logic Design With Xilinx Foundation 2.1i. XESS Corporation, WWW Edition.
- Bolton, M.: Digital Systems Design with Programmable Logic. Addison-Wesley Publishing Company, Cornwall, GB, ISBN 0-201-14545-6, 1990.
- McCluskey, E.J.: LOGIC DESIGN PRICIPLES. Prentice-Hall, USA, ISBN 0-13-539768-5, 1986.
- Cheung, J.Y. - Bredeson, J.G.: MODERN DIGITAL SYSTEMS DESIGN. West Publishing Company, USA, ISBN 0-314-47828-0, 1990.
- Sasao, T.: SWITCHING THEORY FOR LOGIC SYNTHESIS. Kluwer Academic Publishers, Boston, USA, ISBN 0-7923-8456-3, 1999.
- Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE I. University of Alberta, Edmonton, CA, 2003.
- Amaral, J.N.: COMPUTER ORGANIZATION AND ARCHITECTURE II. University of Alberta, Edmonton, CA, 2003.
- Eysselt, M.: Digital Systems Design: Basic Set of Problems 1 (SSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (
**WWW version**). - Eysselt, M.: Digital Systems Design: Basic Set of Problems 2 (MSI Circuits Networks). Student-Text of the FIT, Brno UT, 2003 (
**WWW version**). - Eysselt, M.: Digital Systems Design: Binary Logic Elements (Grafic Symbols for Diagrams). Student-Text of the FIT, Brno UT, 2003 (
**WWW version**). - Eysselt, M.: Digital Systems Design: Laboratory (TTL Family Circuits and Functional Diagrams). Student-Text of the FIT, Brno UT, 2003 (
**WWW version**). - Eysselt, M.: Digital Systems Design: Slides 2003 (Set of Basic Slides). Student-Text of the FIT, Brno UT, 2003.
- Eysselt, M.: Digital Systems Design: Programmable Logic Devices (Foundations & Examples). Student-Text of the FIT Brno UT, FIT Brno UT, 2003 (
**WWW version**).

Fundamental literature

- Harris, D., Harris, S.: Digital Design and Computer Architecture 2nd Edition, Morgan Kaufmann, eBook ISBN: 9780123978165, paperback ISBN: 9780123944245, 2012.
- Wakerly, J. F.: Digital Design: Principles and Practices (4th Edition, Book only) 4th Edition, PEARSON, ISBN: 9788131713662, 8131713660, Edition: 4th Edition, 2008.
- Mano, M. M. R, Ciletti, D.: Digital Design (4th Edition), Prentice-Hall, ISBN:0131989243, 2006.

Syllabus of lectures

- Binary number system: positional notation, conversion of the base, binary codes, binary arithmetic.
- Boolean algebra, logic functions and their representations, logic expressions.
- Reduction methods: Karnaugh maps, Quine-McCluskey tabular method, Petrick's cover function.
- Logic and functional diagrams. Analysis of logic networks behaviour: signal races, hazards.
- Combinational logic: multiplexer, demultiplexer, decoder, coder.
- Combinational logic: comparator, adder, subtractor, arithmetic and logic unit.
- State machines and their representations. Latches and flip-flops.
- Synchronized sequential networks: state coding, optimization and implementation.
- Sequential logic: Registers, counters, shift registers, frequency dividers.
- VHDL language, logic circuits synthesis.
- Design of simple digital circuits: CAD tools, design methodology, FITkit.
- Programmable logic devices.
- Integrated circuits families.

Syllabus of numerical exercises

- Binary number system: positional notation, conversion of the base, binary codes, binary arithmetic.
- Boolean algebra, logic functions and their representations, a behaviour analysis of contact-switch networks.
- Logic expressions. Quine-McCluskey tabular reduction method, Petrick's cover function.
- Reduction methods: Karnaugh maps, logic and functional diagrams.
- Logic functions implementation using logic components.
- Selected logic modules: multiplexer, demultiplexer, encoder, decoder, adder, ALU.
- State machines and their representations. Design of synchronized sequential networks.
- Design of logic networks using programmable logic devices.

Syllabus - others, projects and individual work of students

- Three-hour project.

Progress assessment

*Standard students in Czech Programme:*

1) Mid-term exam: 25 points.

2) Homework and its evaluation in PC laboratory: 20 points.

3) Final exam: 55 points.

The passing boundary for ECTS assessment: 50 points.

*International students:*

1) Test: 20 points.

2) Mid-term exam: 20 points.

3) Final exam: 60 points.

The passing boundary for ECTS assessment: 50 points.

Controlled instruction

Exam prerequisites

Schedule

Course inclusion in study plans