Faculty of Information Technology, BUT

Course details

Advanced Digital Design

NCS Acad. year 2004/2005 Winter semester 6 credits

Combinational and sequential logic design techniques, algorithms, and tools review. Structured design concept. Design strategies. Design decomposition. Design tools. Introduction to VHDL Basic features of VHDL. Simulation and synthesis. Basic VHDL modeling techniques. Algorithmic level design. Register Level Design. HDL-based design techniques. Constrained design. ASIC and PLD design process. Fast prototyping. Modeling for synthesis. Top-down design methodology in VHDL. Design case study. Design automation algorithms. HW/SW co-design.

Guarantor

Language of instruction

Czech

Completion

Examination (written)

Time span

39 hrs lectures, 10 hrs pc labs, 16 hrs projects

Assessment points

40 exam, 20 half-term test, 15 exercises, 25 projects

Department

Lecturer

Subject specific learning outcomes and competences

The students are able to design complex constrained digital systems using contemporary design techniques, hardware description language VHLD, and professional CAD tools.

Learning objectives

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.

Study literature

  • Lecture notes
  • Internet

Fundamental literature

  • James R. Armstrong, F. Gail Gray: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000

Syllabus of lectures

  • Combinational and sequential logic design techniques, algorithms, and tools review.
  • Structured design concept. Design strategies. Design decomposition. Design tools.
  • Introduction to VHDL
  • Basic features of VHDL. Simulation and synthesis.
  • Basic VHDL modeling techniques.
  • Algorithmic level design.
  • Register Level Design.
  • HDL-based design techniques. Constrained design.
  • ASIC and PLD design process. Fast prototyping.
  • Modeling for synthesis.
  • Top-down design methodology in VHDL.
  • Design case study.
  • Design automation algorithms. HW/SW co-design.

Syllabus - others, projects and individual work of students

  • Individual sixteen-hour VHDL project.

Progress assessment

Written mid-term exam, submitted 5 PC lab reports and project in due dates.

Exam prerequisites

Duty credit consists of mid-term exam passing, submitting of 5 PC lab reports and competing the project in due dates.
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