Faculty of Information Technology, BUT

Course details

Diagnosis and Safe Systems

DIA Acad. year 2005/2006 Summer semester 6 credits

Course is not open in this year
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Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.

Guarantor

Language of instruction

Czech

Completion

Credit+Examination (written)

Time span

39 hrs lectures, 10 hrs exercises, 6 hrs laboratories, 10 hrs projects

Assessment points

50 exam, 25 half-term test, 25 projects

Department

Lecturer

Subject specific learning outcomes and competences

Basic approaches to test generation and design for testability.

Generic learning outcomes and competences

Understanding the importance of testing digital computers.

Learning objectives

To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.

Prerequisite kwnowledge and skills

Boolean algebra, principles of computer organization.

Study literature

Lecture notes in electronic format.

Fundamental literature

  • Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design, Computer Science Press, 1990

Syllabus of lectures

  • Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  • Test generation approaches.
  • Funkctional tests.
  • Sequential circuit testing.
  • Test generation at RTL level.
  • Random and pseudorandom test generation.
  • Location sequences.
  • Fault dictionaries.
  • Diagnostic data compression.
  • Design for testability.
  • Built-in diagnosis.
  • Memory testing.
  • Processor and wiring testing.
  • Fail-safe circuits.
  • Fault-tolerance priciples.
  • Diagnostic equipment.

Syllabus of numerical exercises

  • Fault models for TTL, CMOS, PLA and bridge faults.
  • Test generation approaches.
  • Functional tests.
  • Sequential circuit testing.
  • RTL-level test generation.
  • Random and pseudorandom test generation.

Progress assessment

Mid-term exam, labs and a project.

Controlled instruction

Mid-term exam, labs and a project.

Exam prerequisites

Pass a mid-term exam, labs and a project.
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