Faculty of Information Technology, BUT

Course details

Processor Architecture

ACH Acad. year 2009/2010 Winter semester 5 credits

The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on SIMD-style processing and vector processors. The main type of specialized processors are graphical, signal and multimedia processors. The main techniques of parallelization and pipelining of graphical and multimedia operations are explained. Basic compression techniques of graphical data are also discussed.

Guarantor

Language of instruction

Czech

Completion

Credit+Examination (written)

Time span

39 hrs lectures, 13 hrs projects

Assessment points

60 exam, 10 half-term test, 30 projects

Department

Lecturer

Subject specific learning outcomes and competences

Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. The knowledge of architectureand hardware support of graphical and multimedia signals, their coding and compression.

Learning objectives

To familiarize students with architecture of the newest processors exploiting the instruction-level and thread-level parallelism. To clarify the role of a compiler and its  cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical, signal and multimedia processors. To master basic principles of low power architectures, texture compression, mapping algorithms for multiprocessors and data flow processors. 

Prerequisite kwnowledge and skills

Von Neumann computer architecture, memory hierarchy,  microprogramming basics, programming in JSI, compiler's tasks and functions

Study literature

  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 4th Edition, Morgan Kaufman Publishers, Inc., 2007, 1136 p., ISBN 1-55860-596-7.
  • Rao, K.R., Hwang, J.J.: Techniques and Standards for Image, Video, and Audio Coding, Prentice Hall, 1996, 563 p., ISBN 0-13-309907-5.

Fundamental literature

  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 4th Edition, Morgan Kaufman Publishers, Inc., 2006, 1136 p., ISBN 1-55860-596-7.  
  • Rao, K.R., Hwang, J.J.: Techniques and Standards for Image, Video, and Audio Coding, Prentice Hall, 1996, 563 p., ISBN 0-13-309907-5. 
  • Crowley, P. et al.: Network Processor Design. Morgan Kaufman Publ., 2003, 338 p., ISBN 1-55860-875-3.

Syllabus of lectures

  • Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
  • Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  • Advanced superscalar processing techniques. Examples of superscalar CPUs.
  • VLIW processors, hw support for sw pipelining, predication. Binary translation.
  • Data paralelism: vector processors and SIMD-style processing.
  • Thread-level parallelism, multithreaded processors.
  • Network processors.
  • Graphical processors.
  • Signal processors.
  • Techniques for texture compression and multiprocessor mapping.
  • Low power processors.
  • Multimedia processors.
  • Data flow processors.

Syllabus of numerical exercises

Tutorials are not scheduled for this course.

Syllabus - others, projects and individual work of students

  • Superscalar technique of instruction processing (SuperScalar simulator)
  • Performance prediction of a vector processor in solving a specific task.
  • Individual project assignment.

 

Progress assessment

Assessment of three small projects, 4 hours each, and a midterm examination.

Exam prerequisites

To get 20 out of 40 points for projects and midterm examination.

Course inclusion in study plans

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