Thesis Details
Funkční verifikace robotického systému pomocí UVM
One of the currently most used approaches for verification of hardware systems is functional verification. This master thesis describes design and implementation of a verification environment using UVM (Universal Verification Methodology) methodology for verifying the correctness of the robot controller in order to eliminate functional errors and faults of its implementation. The theoretical part of the thesis describes the basic information about functional verification, methodologies for creating verification environments, the SystemVerilog language and fault tolerance methodologies. The next part of thesis focuses on the design of the verification environment, its implementation and the creation of tests used to verify the correctness of the robot controller. Results of verification are discussed and evaluated in the conclusion of this work.
functional verification, SystemVerilog, UVM, fault tolerance
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Hladká Eva, doc. RNDr., Ph.D. (FI MUNI), člen
Holík Lukáš, doc. Mgr., Ph.D. (DITS FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
@mastersthesis{FITMT15154, author = "Stanislav Kraj\v{c}\'{i}r", type = "Master's thesis", title = "Funk\v{c}n\'{i} verifikace robotick\'{e}ho syst\'{e}mu pomoc\'{i} UVM", school = "Brno University of Technology, Faculty of Information Technology", year = 2015, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/15154/" }