Thesis Details
Překladač jazyka VHDL pro potřeby formální verifikace
English title
A VHDL Parser for Formal Verification
Language
Czech
Abstract
The principal goal of this bachelor thesis is to design and implement a parser of VHDL language into graph representation in VAM (Variable Assignment Language). The application is developed for formal verification purposes of VeriFIT research group of the Faculty of Information Technology, Brno University of Technology. The development of the compiler described in this thesis should provide the opportunity to use formal verification techniques to verify hardware designs described in high level design languages, such as VHDL.
Keywords
VHDL parser, Variable Assignment Model, formal verification, Icarus Verilog, data-flow graph, VVP
Department
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
15 June 2015
Reviewer
Committee
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), předseda
Burget Lukáš, doc. Ing., Ph.D. (DCGM FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Křena Bohuslav, Ing., Ph.D. (DITS FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Burget Lukáš, doc. Ing., Ph.D. (DCGM FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Křena Bohuslav, Ing., Ph.D. (DITS FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Citation
MATYÁŠ, Jiří. Překladač jazyka VHDL pro potřeby formální verifikace. Brno, 2015. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2015-06-15. Supervised by Charvát Lukáš. Available from: https://www.fit.vut.cz/study/thesis/17220/
BibTeX
@bachelorsthesis{FITBT17220, author = "Ji\v{r}\'{i} Maty\'{a}\v{s}", type = "Bachelor's thesis", title = "P\v{r}eklada\v{c} jazyka VHDL pro pot\v{r}eby form\'{a}ln\'{i} verifikace", school = "Brno University of Technology, Faculty of Information Technology", year = 2015, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/17220/" }