Thesis Details
Simulátor asembleru x86 pro výuku
Point of this thesis is gain knowledge base of x86 Instruction Set Architecture and x86 assembly language through analysis. Based on this knowledge, design and implement simulation environment in object oriented programming language Java SE8.
This environment will give user option to create code based on conventions and syntax of Netwide Assembler and simulate created code on virtual representation - simulation model, which will imitate behavior of processor implementing instruction set architecture x86.
The result of using this environment should be new knowledge for user about basic function of machine code execution and how this execution alters state of processor, without the need to specially compile created code for use in Debugger and having physical system implementing architecture x86.
Simulator, Simulation, Modeling, Java, Object oriented programming, Netwide Assembler, NASM, assembler, assembler x86, architecture x86
Bařina David, Ing., Ph.D. (DCGM FIT BUT), člen
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Zendulka Jaroslav, doc. Ing., CSc. (DIFS FIT BUT), člen
@bachelorsthesis{FITBT22221, author = "Andrej He\v{s}tera", type = "Bachelor's thesis", title = "Simul\'{a}tor asembleru x86 pro v\'{y}uku", school = "Brno University of Technology, Faculty of Information Technology", year = 2019, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/22221/" }