Thesis Details
Implementace šifrovacích algoritmů v jazyce VHDL
The thesis deals with the design and implementation of the encryption algorithms DES and AES, operating in the CTR mode. The designed modules are implemented in the VHDL language and are mapped in the FPGA Intel Arria 10 SX 480. Algorithms are optimized for maximum throughput using loop unrolling and inner pipelining. The encryption module for DES reaches throughput of 26.2 Gbit/s with the circuit operating 410 MHz, and the module for AES reaches throughput of 34.6 Gbit/s with the circuit operating at 271 MHz. The reached throughput is in the order of thousand times faster than of the same encryption algorithms implemented in software for built-in microprocessors.
encryption, symmetric cipher, block cipher, DES, AES, counter mode, CTR, FPGA, VHDL
Holík Lukáš, doc. Mgr., Ph.D. (DITS FIT BUT), člen
Hradiš Michal, Ing., Ph.D. (DCGM FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
@bachelorsthesis{FITBT23954,
author = "Luk\'{a}\v{s} Frun\v{e}k",
type = "Bachelor's thesis",
title = "Implementace \v{s}ifrovac\'{i}ch algoritm\r{u} v jazyce VHDL",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2021,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/23954/"
}