Thesis Details
Implementace šifrovacích algoritmů v jazyku VHDL
This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.
DES, AES, encryption algorithms, cryptography, FPGA, ECB, embedded systems
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Krejčíček Jaromír, prof. Ing., CSc. (UNOB), člen
@mastersthesis{FITMT4730,
author = "Petr Ko\v{z}en\'{y}",
type = "Master's thesis",
title = "Implementace \v{s}ifrovac\'{i}ch algoritm\r{u} v jazyku VHDL",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2008,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/4730/"
}