Thesis Details
Implementace generického procesoru v FPGA
This thesis studies processor architectures suitable for embedded processors. This includes Transport Triggered Architectures (TTA). TTA is programmed by specifying data transport; operations are triggered as a side effect of data transports. In traditional Operation Triggered Architectures (OTA) requested operations are determined by program. Data transports are handled internally by hardware so it's impossible to control and optimize data transfer by compiler. This approach brings an advantage of hardware and software aspects. The aim of this thesis is to design and implement a sample TTA processor in VHDL followed by realization in FPGA. This processor is designed in a generic manner, i.e. customized by set of generic parameters such as data width, number of buses, etc.
transport triggered architectures, VLIW, processor architectures, VHDL, COMBO6X, FPGA, Virtex-II Pro
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Krejčíček Jaromír, prof. Ing., CSc. (UNOB), člen
Křena Bohuslav, Ing., Ph.D. (DITS FIT BUT), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
@mastersthesis{FITMT4740,
author = "Petr Miku\v{s}ek",
type = "Master's thesis",
title = "Implementace generick\'{e}ho procesoru v FPGA",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2007,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/4740/"
}