Thesis Details
Návrh a implementace kodéru a dekodéru Iwadariho kódu
This thesis deals with the design, the implementation and oncoming testing of circuits implementing the encoder and the decoder of the Iwadari code with universal correction ability. The design according to the theory of forward error correction systems is well-founded by mathematic modeling. Describing of the implementation prefers VHDL language. The implemented encoder and decoder were simulated in specialized development environments to verify their correct operation. Final demonstrational physical implementation of testing connection of the encoder and the decoder in experimental educational platform FIT-kit was made to show their function and mechanism.
forward error correction, Iwadari´s encoder, Iwadari´s decoder, FPGA, VHDL, FIT-kit
Černocký Jan, prof. Dr. Ing. (DCGM FIT BUT), člen
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), člen
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Jedlička Petr, Ing., Ph.D. (Mendelu), člen
Peringer Petr, Dr. Ing. (DITS FIT BUT), člen
@bachelorsthesis{FITBT5171,
author = "Jan K\v{r}iv\'{a}nek",
type = "Bachelor's thesis",
title = "N\'{a}vrh a implementace kod\'{e}ru a dekod\'{e}ru Iwadariho k\'{o}du",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2007,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/5171/"
}