Thesis Details

Návrh paměti CACHE pro síťové aplikace

Bachelor's Thesis Student: Soľanka Lukáš Academic Year: 2006/2007 Supervisor: Kořenek Jan, doc. Ing., Ph.D.
English title
CACHE Memory Design for Network Applications
Language
Czech
Abstract

This thesis deals with design and implementation of generic cache memory for a wide range of network applications. Firstly, aspects with influence on performance are discussed. Then architecture is proposed and implemented with respect to the given technology. The main selectable parameters of  the design are: data path width, line size, associativity, number of lines  and replacement policy. Cache is also pipelined and therefore is able to process one request for reading or writing every clock cycle. The resulting component has been thoroughly simulated to verify its functionality and finally, its operation has also been tested in hardware on the Combo6X  board.

Keywords

cache, network, FPGA

Department
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
12 June 2007
Reviewer
Committee
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT), předseda
Černocký Jan, prof. Dr. Ing. (DCGM FIT BUT), člen
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), člen
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Jedlička Petr, Ing., Ph.D. (Mendelu), člen
Peringer Petr, Dr. Ing. (DITS FIT BUT), člen
Citation
SOĽANKA, Lukáš. Návrh paměti CACHE pro síťové aplikace. Brno, 2007. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2007-06-12. Supervised by Kořenek Jan. Available from: https://www.fit.vut.cz/study/thesis/5230/
BibTeX
@bachelorsthesis{FITBT5230,
    author = "Luk\'{a}\v{s} So\'{l}anka",
    type = "Bachelor's thesis",
    title = "N\'{a}vrh pam\v{e}ti CACHE pro s\'{i}\v{t}ov\'{e} aplikace",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2007,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/5230/"
}
Back to top