Thesis Details

Hardwarová akcelerace analýzy a extrakce položek z hlaviček paketů

Bachelor's Thesis Student: Polčák Libor Academic Year: 2007/2008 Supervisor: Kořenek Jan, doc. Ing., Ph.D.
English title
Hardware Acceleration of Analysis and Header Field Extraction
Language
Czech
Abstract

This work deals with packet analysis and processing for high speed networks using FPGA.Model of the analysis and hardware architecture have been proposed. Protocols can bespecified in XML. Automated tool is able to convert this specification to VHDL. As mul-tiple bytes and protocol headers are processed within one clock cycle simultaneously, theproposed unit is able to handle packet processing on 10 Gbps speed and higher.

Keywords

Network, packet analysis, header field extraction, FPGA

Department
Department of Computer Systems FIT BUT
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
9 June 2008
Reviewer
Tobola Jiří, Ing.
Committee
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Malo Roman, Ing., Ph.D. (Mendelu), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT), člen
Citation
POLČÁK, Libor. Hardwarová akcelerace analýzy a extrakce položek z hlaviček paketů. Brno, 2008. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2008-06-09. Supervised by Kořenek Jan. Available from: https://www.fit.vut.cz/study/thesis/5232/
BibTeX 
@bachelorsthesis{FITBT5232,
    author = "Libor Pol\v{c}\'{a}k",
    type = "Bachelor's thesis",
    title = "Hardwarov\'{a} akcelerace anal\'{y}zy a extrakce polo\v{z}ek z hlavi\v{c}ek paket\r{u}",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2008,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/5232/"
}

Theses

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