Thesis Details

Algoritmy souběžného technického a programového návrhu

Master's Thesis Student: Vlach Jan Academic Year: 2006/2007 Supervisor: Fučík Otto, doc. Dr. Ing.
English title
Hardware-Software Codesign Algorithms
Language
Czech
Abstract

This master's thesis deals with a parallel design of the program and a technical equipment of embedded systems. It involves both a general description of the whole process and an illustration of the design, a simulation and implementation of the FIR filter. It also includes a description of the proposed program Polis and the simulation system Ptolemy. The conclusion of the project is devoted to a generation of simulation models in VHDL language incl. a subsequent synthesis.

Keywords

Hardware-software codesign, hardware-software cosimulation, specification language Esterel, program Polis, simulation system Ptolemy, VHDL

Department
Degree Programme
Electrical Engineering and Computer Science, Field of Study Computer Science and Engineering
Files
Status
defended, grade D
Date
29 August 2007
Reviewer
Committee
Hruška Tomáš, prof. Ing., CSc. (DIFS FIT BUT), předseda
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT), člen
Kreslíková Jitka, doc. RNDr., CSc. (DIFS FIT BUT), člen
Motyčka Arnošt, doc. Ing., CSc. (Mendelu), člen
Zendulka Jaroslav, doc. Ing., CSc. (DIFS FIT BUT), člen
Citation
VLACH, Jan. Algoritmy souběžného technického a programového návrhu. Brno, 2007. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2007-08-29. Supervised by Fučík Otto. Available from: https://www.fit.vut.cz/study/thesis/5348/
BibTeX
@mastersthesis{FITMT5348,
    author = "Jan Vlach",
    type = "Master's thesis",
    title = "Algoritmy soub\v{e}\v{z}n\'{e}ho technick\'{e}ho a programov\'{e}ho n\'{a}vrhu",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2007,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/5348/"
}
Back to top