Thesis Details

Akcelerace grafických operací s využitím FPGA

Master's Thesis Student: Čapka Ladislav Academic Year: 2006/2007 Supervisor: Vašíček Zdeněk, doc. Ing., Ph.D.
English title
Acceleration of Graphics Operations by Means FPGA
Language
Czech
Abstract

This term project is aimed on analysis of graphic pipeline which can rasterize required picture. Document is specialized to drawing algorithms that are used in rasterization block. Major aim of this project is describing of rasterization algorithms that can be implemented on hardware. Type of aimed hardware is field-programmable gate array FPGA.

Keywords

graphic hardware, FPGA, rasterization, rasterization algorithms, base objects, interpolation, NURBS, Bézier

Department
Degree Programme
Information Technology, Field of Study Computer Graphics and Multimedia
Files
Status
defended, grade A
Date
20 June 2007
Reviewer
Committee
Zemčík Pavel, prof. Dr. Ing. (DCGM FIT BUT), předseda
Černocký Jan, prof. Dr. Ing. (DCGM FIT BUT), člen
Fučík Otto, doc. Dr. Ing. (DCSY FIT BUT), člen
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Křena Bohuslav, Ing., Ph.D. (DITS FIT BUT), člen
Šlapal Josef, prof. RNDr., CSc. (DADM FME BUT), člen
Citation
ČAPKA, Ladislav. Akcelerace grafických operací s využitím FPGA. Brno, 2007. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2007-06-20. Supervised by Vašíček Zdeněk. Available from: https://www.fit.vut.cz/study/thesis/5484/
BibTeX
@mastersthesis{FITMT5484,
    author = "Ladislav \v{C}apka",
    type = "Master's thesis",
    title = "Akcelerace grafick\'{y}ch operac\'{i} s vyu\v{z}it\'{i}m FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2007,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/5484/"
}
Back to top