Thesis Details

Návrh a implementace prostředků pro zvýšení výkonu procesoru

Master's Thesis Student: Zlatohlávková Lucie Academic Year: 2006/2007 Supervisor: Strnadel Josef, Ing., Ph.D.
English title
Design and Implementation of Mechanisms for Enhancing Performance of CPU
Language
Czech
Abstract

This master‘s thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is enriched by modern components in processor architecture such as pipelining, cache memory and branch prediction. The processor has been made in VHDL programming language and was simulated in ModelSim simulation tool.

Keywords

Architecture, Computer, Processor, Instruction, Pipelining, Branch prediction, Cache memory.

Department
Department of Computer Systems FIT BUT
Degree Programme
Electrical Engineering and Computer Science, Field of Study Computer Science and Engineering
Files
Status
defended, grade D
Date
18 June 2007
Reviewer
Sekanina Lukáš, prof. Ing., Ph.D.
Committee
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), předseda
Eysselt Miloš, Ing., CSc. (DCSY FIT BUT), člen
Kreslíková Jitka, doc. RNDr., CSc. (DIFS FIT BUT), člen
Rybička Jiří, doc. Ing. Dr. (Mendelu), člen
Zbořil František V., doc. Ing., CSc. (DITS FIT BUT), člen
Citation
ZLATOHLÁVKOVÁ, Lucie. Návrh a implementace prostředků pro zvýšení výkonu procesoru. Brno, 2007. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2007-06-18. Supervised by Strnadel Josef. Available from: https://www.fit.vut.cz/study/thesis/5668/
BibTeX 
@mastersthesis{FITMT5668,
    author = "Lucie Zlatohl\'{a}vkov\'{a}",
    type = "Master's thesis",
    title = "N\'{a}vrh a implementace prost\v{r}edk\r{u} pro zv\'{y}\v{s}en\'{i} v\'{y}konu procesoru",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2007,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/5668/"
}

Theses

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