Thesis Details

Návrh pokročilé architektury procesoru ve VHDL

Semestral project Student: Novotný Jaroslav Academic Year: 2007/2008 Supervisor: Straka Martin, Ing., Ph.D.
English title
VHDL Design of Advance CPU with CACHE
Language
Czech
Abstract

The aim of this paper is to design and partially implement an advanced processor architecture in the VHDL language. It describes basic architectures of processors and CACHE memories. It also deals with the serial implementation of instructions and briefly describes the VHDL language. Finally, a design of a simple VHDL language processor and its upgrade by adding serial implementation of instructions is presented. A possiblity to use the data and instruction CACHE memory is discussed too.

Keywords

Processor, pipelining, cache, Two-Way Set Associative Cache, VHDL

Department
Degree Programme
Files
Status
defended
Date
9 January 2008
Citation
NOVOTNÝ, Jaroslav. Návrh pokročilé architektury procesoru ve VHDL. Brno, 2008. Semestral project. Brno University of Technology, Faculty of Information Technology. 2008-01-09. Supervised by Straka Martin. Available from: https://www.fit.vut.cz/study/thesis/6235/
Back to top