Thesis Details

Testování spojů a externích paměťových komponent v FPGA

Master's Thesis Student: Louda Martin Academic Year: 2007/2008 Supervisor: Martínek Tomáš, doc. Ing., Ph.D.
English title
Testing of Wires and External Memory Components in FPGA
Language
Czech
Abstract

This work deals with COMBO2 card interconnect and memory devices testing. In the beginning of the paper, some existing testing algorithms for interconnect and RAM memories testing are introduced. This work is devoted to proposal of generic architecture for interconnect and memory devices testing. The proposed architecture is optimized for FPGA implementation.

Keywords

interconnect testing, wires testing, RAM memory testing, March test, FPGA, VHDL, Handel-C, COMBO2

Department
Degree Programme
Information Technology, Field of Study Computer Systems and Networks
Files
Status
defended, grade A
Date
18 June 2008
Reviewer
Committee
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Krejčíček Jaromír, prof. Ing., CSc. (UNOB), člen
Citation
LOUDA, Martin. Testování spojů a externích paměťových komponent v FPGA. Brno, 2008. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2008-06-18. Supervised by Martínek Tomáš. Available from: https://www.fit.vut.cz/study/thesis/6599/
BibTeX
@mastersthesis{FITMT6599,
    author = "Martin Louda",
    type = "Master's thesis",
    title = "Testov\'{a}n\'{i} spoj\r{u} a extern\'{i}ch pam\v{e}\v{t}ov\'{y}ch komponent v FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2008,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/6599/"
}
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