Thesis Details

Generování procesních elementů pro FPGA

Bachelor's Thesis Student: Lengál Ondřej Academic Year: 2007/2008 Supervisor: Žádník Martin, Ing., Ph.D.
English title
Automated Generating of Processing Elements for FPGA
Language
Czech
Abstract

Some information processing applications, such as computer networks monitoring, need to continuously perform processing of rapidly incoming data. As the speed of the incoming data increases, it is desirable to perform the processing in the hardware. This work proposes a configuration system that generates a VHDL specification of a hardware data processing circuit based on a user-provided definition of data and computation operations. The system focuses on network traffic monitoring in multi-gigabit computer networks.

Keywords

high-level synthesis, scheduling, flow processing, firmware generation, FPGA, network monitoring

Department
Department of Computer Systems FIT BUT
Degree Programme
Information Technology
Files
Status
defended, grade A
Date
9 June 2008
Reviewer
Tobola Jiří, Ing.
Committee
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Hrubý Martin, Ing., Ph.D. (DITS FIT BUT), člen
Malo Roman, Ing., Ph.D. (Mendelu), člen
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS FIT BUT), člen
Strnadel Josef, Ing., Ph.D. (DCSY FIT BUT), člen
Citation
LENGÁL, Ondřej. Generování procesních elementů pro FPGA. Brno, 2008. Bachelor's Thesis. Brno University of Technology, Faculty of Information Technology. 2008-06-09. Supervised by Žádník Martin. Available from: https://www.fit.vut.cz/study/thesis/6664/
BibTeX 
@bachelorsthesis{FITBT6664,
    author = "Ond\v{r}ej Leng\'{a}l",
    type = "Bachelor's thesis",
    title = "Generov\'{a}n\'{i} procesn\'{i}ch element\r{u} pro FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2008,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/6664/"
}

Theses

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