Project Details

Automatizovaný návrh hardwarových akcelerátorů pro strojového učení zohledňující výpočetní zdroje

Project Period: 1. 1. 2021 - 31. 12. 2023

Project Type: grant

Code: GA21-13001S

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Automated design of hardware accelerators for resource-aware machine learning

evolutionary algorithm, deep neural network, machine learning, accelerator, digital circuit, power consumption, evolvable hardware


Machine learning (ML), particularly the technology based on deep neural networks (DNNs), has already reached and overcome human-level capabilities in many domains. A significant future use of trained ML models is expected in battery powered devices, where the major constraints are energy and the amount of resources available on a chip. The current approach to the DNN design is based on semi-automated simplifying of a network which is created by a human expert who could only partly reflect all hardware implementation aspects. In this project, the aim is to propose and evaluate a methodology for the highly automated design of hardware accelerators of DNNs (and other selected ML methods) that show excellent trade-offs between the output quality, energy and resources used on a single chip. Our approach is based on evolutionary design of such implementations of DNNs (and other ML systems) that reflect a target hardware platform. The proposed method will be evaluated on standard benchmark problems such as image classification and on automated assessment of Parkinsons disease.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY FIT VUT) , research leader
Drahošová Michaela, Ing., Ph.D. (UPSY FIT VUT)
Hurta Martin, Ing. (FIT VUT)
Hurta Martin, Ing. (UPSY FIT VUT)
Matoušek Jiří, Ing., Ph.D. (UPSY FIT VUT)
Mrázek Vojtěch, Ing., Ph.D. (UPSY FIT VUT)
Piňos Michal, Ing. (UPSY FIT VUT)
Vašíček Zdeněk, doc. Ing., Ph.D. (UPSY FIT VUT)
Žufan Petr, Ing. (UPSY FIT VUT)





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