Metodika a prostředky pro analýzu testovatelnosti digitálních obvodů
Project Period: 1. 1. 1998 - 31. 3. 2006
Project Type: grant
Agency: Czech Science Foundation
digital circuit diagnostics-testability analysis
The goal of the research activities is to develop and implement testability analysis methodology such that the concepts and algorithms could be used in any design environment, to offer an alternative to the full scan approach. It is supposed that the structure of the circuit under analysis will be transformed into a database representing the diagnostic features of the circuit. The applicability will be verified on circuits described in VHDL language and on ISCAS benchmark circuits.