Project Details

Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu

Project Period: 1. 1. 2001 - 31. 12. 2003

Project Type: grant

Code: GA102/01/1531

Agency: Czech Science Foundation


English title
Formal Approaches in Digital Design Diagnostics - Testable Design Verification

testable design synthesis, digital circuit testability verification


The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topics of testability are evaluated simultaneously with the synthesis - e. g. full scan, partial scan or BIST methods. Different aspects of the circuit design are evaluated and the controllability/observability of the inputs/outputs of internal elements of the unit under design is an important feature. The diagnostic methodologies utilized during the circuit synthesis are based on heuristic approaches during which the structure of the circuit is analysed. These heuristic approaches are different for different types of circuits.The goal of this project is the development of formal tools which can be used to represent diagnostic features of a circuit and its internal elements, based on theory of sets, theory of graphs and mathematical logic concepts. The applicability of the formal tools will be verified on benchmark circuits and on circuits developed for practical applications. Together with this main theme the research into analytical approaches will be made. The results gained for both approaches will be currently compared. The possibility of combining both approaches will also be verified.

Team members
Kotásek Zdeněk, Doc. Ing., CSc. (UIVT-VVS FEI VUT) , research leader
Drábek Vladimír, doc. Ing., CSc. (UIVT FEI VUT) , team leader
Růžička Richard, Ing. (UIVT FEI VUT) , team leader
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY FIT VUT) , team leader
Strnadel Josef, Ing. (UIVT FEI VUT) , team leader
Zbořil František, Doc. Ing., CSc. (UIVT FEI VUT) , team leader




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