Publication Details

Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

SÁNCHEZ-CLEMENTE Antonio José, ENTRENA Luis, HRBÁČEK Radek and SEKANINA Lukáš. Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Transactions on Reliability, vol. 65, no. 4, 2016, pp. 1871-1883. ISSN 0018-9529. Available from: http://dx.doi.org/10.1109/TR.2016.2604918
Czech title
Maskování chyb pomocí aproximovaných logických obvodů: Porovnání pravděpodobnostního a evolučního přístupu
Type
journal article
Language
english
Authors
Sánchez-Clemente Antonio José (UC3M)
Entrena Luis (UC3M)
Hrbáček Radek, Ing. (DCSY FIT BUT)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)
URL
Keywords


Approximate logic circuit, error mitigation, evolutionary computing, single-event transient (SET), single-event upset (SEU)

Published
2016
Pages
1871-1883
Journal
IEEE Transactions on Reliability, vol. 65, no. 4, ISSN 0018-9529
Publisher
Institute of Electrical and Electronics Engineers
DOI
10.1109/TR.2016.2604918
UT WoS
000391284600019
EID Scopus
2-s2.0-84990841014
BibTeX 
@ARTICLE{FITPUB10995,
   author = "Jos\'{e} Antonio S\'{a}nchez-Clemente and Luis Entrena and Radek Hrb\'{a}\v{c}ek and Luk\'{a}\v{s} Sekanina",
   title = "Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches",
   pages = "1871--1883",
   journal = "IEEE Transactions on Reliability",
   volume = 65,
   number = 4,
   year = 2016,
   ISSN = "0018-9529",
   doi = "10.1109/TR.2016.2604918",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10995"
}
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