Result Details

HLS-based Fault Tolerance Approach for SRAM-based FPGAs

LOJDA, J.; PODIVÍNSKÝ, J.; KRČMA, M.; KOTÁSEK, Z. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 301-302. ISBN: 978-1-5090-5602-6.
Type
conference paper
Language
English
Authors
Lojda Jakub, Ing., Ph.D., DCSY (FIT)
Podivínský Jakub, Ing., Ph.D., DCSY (FIT)
Krčma Martin, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

This paperpresents an approach to fault-tolerant systems design and synthesis based onHigh-level Synthesis (HLS). A description and evaluation of the impacts of HLS optimizationmethods are shown as well. The higher reliability is achieved through modificationof input description in the C++ programming language on which the HLS synthesistools are based on. Our work targets SRAM-based FPGAs, which are prone toSingle Event Upsets (SEUs). For the evaluation of impacts of HLS optimizationmethods we use our evaluation platform, which allows us to test fault toleranceproperties of the Design Under Test (DUT). The evaluation platform is based onfunctional verification combined with fault injection.

Keywords

High Level Synthesis
CatapultC
Fault Tolerance
Robot Controller

Published
2016
Pages
301–302
Proceedings
Proceedings of the 2016 International Conference on Field Programmable Technology
Conference
The 2016 International Conference on Field-Programmable Technology
ISBN
978-1-5090-5602-6
Publisher
IEEE Computer Society
Place
Xi'an
DOI
10.1109/FPT.2016.7929561
UT WoS
000402988900057
EID Scopus
2-s2.0-85021451935
BibTeX 
@inproceedings{BUT131020,
  author="Jakub {Lojda} and Jakub {Podivínský} and Martin {Krčma} and Zdeněk {Kotásek}",
  title="HLS-based Fault Tolerance Approach for SRAM-based FPGAs",
  booktitle="Proceedings of the 2016 International Conference on Field Programmable Technology",
  year="2016",
  pages="301--302",
  publisher="IEEE Computer Society",
  address="Xi'an",
  doi="10.1109/FPT.2016.7929561",
  isbn="978-1-5090-5602-6",
  url="https://www.fit.vut.cz/research/publication/11275/"
}
Files
Projects
Algorithms, Design Methods, and Many-Core Execution Platform for Low-Power Massive Data-Rate Video and Image Processing, MŠMT, Společné technologické iniciativy, 7H14002, start: 2014-04-01, end: 2017-06-30, completed
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, start: 2016-01-01, end: 2020-12-31, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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