Faculty of Information Technology, BUT

Publication Details

Relaxed equivalence checking: a new challenge in logic synthesis

VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-0472-4.
Czech title
Přibližná ekvivalence: nový problém logické syntézy
Type
conference paper
Language
english
Authors
Keywords
equivalence checking, relaxed equivalence checking, logic circuits, formal techniques, sat solvers, binary decision diagrams
Abstract
The functional equivalence has always been the integral part of virtually every logic synthesis tool. The formal equivalence checking represents a key process that helps logic synthesis tool guarantee that two representations of a circuit design exhibit exactly the same behavior. Among others,equivalence checking is routinely applied to prove that a synthesized digital circuit is logically equivalent to the RTL source code. Although formal equivalence checking has matured greatly during the last two decades and designs with millions of gates can be handled and verified in reasonable time, a new challenge has emerged with the recent advent of approaches addressing the problem of synthesis of approximate circuits.
Published
2017
Pages
1-6
Proceedings
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems
Conference
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2017, Hotel Taschenbergpalais Kempinski, Dresden, DE
ISBN
978-1-5386-0472-4
Publisher
IEEE Computer Society
Place
Dresden, DE
DOI
BibTeX
@INPROCEEDINGS{FITPUB11410,
   author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek",
   title = "Relaxed equivalence checking: a new challenge in logic synthesis",
   pages = "1--6",
   booktitle = "Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit \& Systems",
   year = 2017,
   location = "Dresden, DE",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-5386-0472-4",
   doi = "10.1109/DDECS.2017.7968435",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11410"
}
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