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Automation of Processor Verification Using Recurrent Neural Networks

FAJČÍK Martin, ZACHARIÁŠOVÁ Marcela and SMRŽ Pavel. Automation of Processor Verification Using Recurrent Neural Networks. In: 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV). Austin, Texas: Institute of Electrical and Electronics Engineers, 2017, pp. 15-20. ISBN 978-1-5386-3351-9. Available from: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8396943
Czech title
Automatizace verifikace pomocí neuronových sítí
Type
conference paper
Language
english
Authors
URL
Keywords
Functional Verification, Automation of Verification, Neural network, Recurrent Neural Network, Hopfield Net-work,  UVM,  Coverage-Driven  Verification,  Optimization  Problem,  Combinatorial  Optimization
Abstract
When  considering  simulation-based  verification  of processors, the current trend is to generate stimuli using pseudo-random  generators  (PRGs),  apply  them  to  the  processor  inputs and monitor the achieved coverage of its functionality in order to determine  verification  completeness.  Stimuli  can  have  different forms, for example, they can be represented by bit vectors applied to  the  input  ports  of  the  processor  or  by  programs  that  are loaded  directly  into  the  program  memory.  In  this  paper,  we propose  a  new  technique  dynamically  altering  constraints  for PRG  via  recurrent  neural  network,  which  receives  a  coverage feedback from the simulation of design under verification. For the demonstration purposes we used processors provided by Codasip as  their  coverage  state  space  is  reasonably  big  and  differs  for various  kinds  of  processors.  Nevertheless,  techniques  presented in  this  paper  are  widely  applicable.  The  results  of  experiments show that not only the coverage closure is achieved much sooner, but we are able to isolate a small set of stimuli with high coverage that  can  be  used  for  running  regression  tests.
Published
2017
Pages
15-20
Proceedings
2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV)
Conference
Microprocessor/SoC Test, Security & Verification 2017, Austin, Texas, US
ISBN
978-1-5386-3351-9
Publisher
Institute of Electrical and Electronics Engineers
Place
Austin, Texas, US
DOI
BibTeX
@INPROCEEDINGS{FITPUB11512,
   author = "Martin Faj\v{c}\'{i}k and Marcela Zachari\'{a}\v{s}ov\'{a} and Pavel Smr\v{z}",
   title = "Automation of Processor Verification Using Recurrent Neural Networks",
   pages = "15--20",
   booktitle = "2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV)",
   year = 2017,
   location = "Austin, Texas, US",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-5386-3351-9",
   doi = "10.1109/MTV.2017.15",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11512"
}
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