Faculty of Information Technology, BUT

Publication Details

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 80-86. ISBN 978-1-5386-5709-6.
Czech title
Odolnost proti poruchám systémů generovaných principy vysokoúrovňové syntézy
Type
conference paper
Language
english
Authors
Keywords
High-Level Synthesis, Fault Tolerance Evaluation, Fault Tolerance Estimation Framework, Catapult C, C++, VHDL.
Abstract
During the last decades, electronic systems became an important matter of controlling many critical processes. However, those critical processes often require increased reliability. This requirement puts pressure on system developers to make systems reliable. Because of ever growing chip-level integration, capabilities of electronic systems are expanding, and, thus, leading to more complex system architectures, significantly increasing the number of man-hours needed to develop such systems. Many people believe the solution is to move the development to a higher level of abstraction (e.g. an algorithm level) and use the so-called High-Level Synthesis (HLS) for this purpose. In this research, we aimed towards a decision, whether the usage of HLS impacts the resulting reliability properties of the system, and, thus, whether the HLS-generated system matches reliability properties of its corresponding VHDL-implemented version. We found out that, for the selected set of circuits, HLS performs better in terms of resource consumption, but, also, which we consider surprising, in terms of reliability. For the selected set, HLS achieved better reliability by 3.03 percentage points in contrast to the classical approach utilizing a traditional Hardware Description Language (HDL). In these experiments, no redundancy was intentionally inserted into benchmarking circuits.
Published
2018
Pages
80-86
Proceedings
Proceedings of IEEE East-West Design & Test Symposium
Conference
16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM, Kazan, RU
ISBN
978-1-5386-5709-6
Publisher
IEEE Computer Society
Place
Kazan, RU
DOI
BibTeX
@INPROCEEDINGS{FITPUB11752,
   author = "Jakub Lojda and Jakub Podiv\'{i}nsk\'{y} and Zden\v{e}k Kot\'{a}sek",
   title = "Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis",
   pages = "80--86",
   booktitle = "Proceedings of IEEE East-West Design \& Test Symposium",
   year = 2018,
   location = "Kazan, RU",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-5386-5709-6",
   doi = "10.1109/EWDTS.2018.8524631",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11752"
}
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