Publication Details

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš and KOTÁSEK Zdeněk. Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study. In: Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019, pp. 20-21. ISBN 978-80-01-06607-2. Available from:
Czech title
Případová studie výpočtu průniku multidimenzionálních Pareto front v optimalizaci procesoru
conference paper

Pareto optimization, Pareto frontier, processor optimization, ASIP.


Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a processor is used in multiple designs. The gal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Proceedings of the 7th Prague Embedded Systems Workshop
The 7th Prague Embedded Systems Workshop, Roztoky u Prahy, CZ
Czech Technical University
Roztoky u Prahy, CZ
   author = "Jakub Podiv\'{i}nsk\'{y} and Ond\v{r}ej \v{C}ekan and Martin Kr\v{c}ma and Radek Burget and Tom\'{a}\v{s} Hru\v{s}ka and Zden\v{e}k Kot\'{a}sek",
   title = "Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study",
   pages = "20--21",
   booktitle = "Proceedings of the 7th Prague Embedded Systems Workshop",
   year = 2019,
   location = "Roztoky u Prahy, CZ",
   publisher = "Czech Technical University",
   ISBN = "978-80-01-06607-2",
   language = "english",
   url = ""
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