Result Details
Test Controller Design Based on VHDL Source File Analysis
MIKA, D.; KOTÁSEK, Z.; STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2.
Type
conference paper
Language
English
Authors
Abstract
In the paper the process of test controller design and synthesis onregister transfer level (RTL) is described. The sequence of control,address and data signals together with circuit structure for which thetest controller is designed are the input information of the problem.The methodology of transforming an RTL circuit into a labelled directedgraph and then into VHDL source code will be presented. The ideas oftest controller synthesis based on this information will be explicitlyshown.
Keywords
Register Transfer Level, Data Transporter, Data Processor, The Unit Under Analysis
Published
2002
Pages
135–141
Proceedings
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
Series
VIENALA Press, Edition: 55
Conference
Electronic Computers and Informatics'2002
ISBN
80-7099-879-2
Publisher
The University of Technology Košice
Place
Letná 42, 040 01 TU Košice
BibTeX
@inproceedings{BUT10249,
author="Daniel {Mika} and Zdeněk {Kotásek} and Josef {Strnadel}",
title="Test Controller Design Based on VHDL Source File Analysis",
booktitle="Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002",
year="2002",
series="VIENALA Press, Edition: 55",
pages="135--141",
publisher="The University of Technology Košice",
address="Letná 42, 040 01 TU Košice",
isbn="80-7099-879-2"
}
Projects
Formal Approaches in Digital Design Diagnostics - Testable Design Verification, GACR, Standardní projekty, GA102/01/1531, start: 2001-01-01, end: 2003-12-31, completed
Research groups
Departments