Result Details

Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs

KOŘENEK, J.; SEKANINA, L. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2005. p. 46-55. ISBN: 978-3-540-28736-0.
Type
conference paper
Language
English
Authors
Kořenek Jan, doc. Ing., Ph.D., FIT (FIT), DCSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Abstract

A specialized architecture was developed and evaluated to evolve relatively
large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on the same FPGA. We evolved sorting networks up to N=28. The evolution of the largest sorting networks requires 10 hours in FPGA running at 100 MHz. The experiments were performed using COMBO6 card.

Keywords

Evolution, FPGA, sorting network

URL
Published
2005
Pages
46–55
Proceedings
Evolvable Systems: From Biology to Hardware
Series
Lecture Notes in Computer Science
Volume
3637
Conference
International Conference on Evolvable Systems: From Biology to Hardware
ISBN
978-3-540-28736-0
Publisher
Springer Verlag
Place
Berlin
BibTeX 
@inproceedings{BUT33687,
  author="Jan {Kořenek} and Lukáš {Sekanina}",
  title="Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs",
  booktitle="Evolvable Systems: From Biology to Hardware",
  year="2005",
  series="Lecture Notes in Computer Science",
  volume="3637",
  pages="46--55",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-28736-0",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ices05/sn.pdf"
}
Projects
Evolvable hardware based applications design methods, GACR, Postdoktorandské granty, GP102/03/P004, start: 2003-01-01, end: 2005-12-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Reconfigurable Architecture Research Group (RG FPGA)
Departments
Department of Computer Systems (DCSY)
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