Result Details
Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space
        STRNADEL, J. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 161-162.  ISBN: 1-4244-0184-4.
    
                Type
            
        
                conference paper
            
        
                Language
            
        
                English
            
        
            Authors
            
        
                Strnadel Josef, Ing., Ph.D., DCSY (FIT)
            
        
                    Abstract
            
        In the paper, novel sessionless approach to test-schedulling is presented. It utilizes so-called STEPs during special random-search based scheduling algorithm. The algorithm explores the state-space of so-called i-schedules whereas an i-schedule is an integer-vector encoded test-schedule represented by n-touple of STEPs. Proposed algorithm tries to link tests to STEPs in such a way there are no resource sharing conflicts in the best-found test schedule and hopefully, test schedule constraints are met maximally at minimal time and TAM values.
                Keywords
            
        test scheduling, power constraint, test access mechanism, sessionless, test application graph
                Published
            
            
                    2006
                    
                
            
                    Pages
                
            
                        161–162
                
            
                        Proceedings
                
            
                    Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
                
            
                    Conference
                
            
                    IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
                
            
                    ISBN
                
            
                    1-4244-0184-4
                
            
                    Publisher
                
            
                    Czech Technical University Publishing House
                
            
                    Place
                
            
                    Prague
                
            
                    BibTeX
                
            @inproceedings{BUT22186,
  author="Josef {Strnadel}",
  title="Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2006",
  pages="161--162",
  publisher="Czech Technical University Publishing House",
  address="Prague",
  isbn="1-4244-0184-4"
}
                Projects
            
        
        
            
        
    
    
        Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed
                
Optimizing Methods in Digital Systems Diagnosis, GACR, Postdoktorandské granty, GP102/05/P193, start: 2005-01-01, end: 2007-12-31, completed
        Optimizing Methods in Digital Systems Diagnosis, GACR, Postdoktorandské granty, GP102/05/P193, start: 2005-01-01, end: 2007-12-31, completed
                Research groups
            
        
                Dependable Digital Systems Research Group (RG DEPSYS)
            
        
                Departments