Faculty of Information Technology, BUT

Publication Details

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

OTERO Andres, SALVADOR Ruben, MORA Javier, DE la Torre Eduardo, RIESGO Teresa and SEKANINA Lukáš. A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems. In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2011, pp. 336-343. ISBN 978-1-4577-0599-1.
Czech title
Architektura rekonfigurovatelného 2D bloku pro vyvíjející se adaptivní systémy v FPGA
Type
conference paper
Language
english
Authors
Otero Andres (UPN)
Salvador Ruben (UPN)
Mora Javier (UPN)
De la Torre Eduardo (UPN)
Riesgo Teresa (UPN)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT)
Keywords
field programmable gate array, adaptive hardware, dynamic partial reconfiguration, IP core, evolvable hardware
Abstract
Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.
Published
2011
Pages
336-343
Proceedings
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems
Conference
NASA/ESA Conference on Adaptive Hardware and Systems 2011, San Diego, US
ISBN
978-1-4577-0599-1
Publisher
IEEE Computer Society
Place
Los Alamitos, US
BibTeX
@INPROCEEDINGS{FITPUB9681,
   author = "Andres Otero and Ruben Salvador and Javier Mora and Eduardo Torre la De and Teresa Riesgo and Luk\'{a}\v{s} Sekanina",
   title = "A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems",
   pages = "336--343",
   booktitle = "Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems",
   year = 2011,
   location = "Los Alamitos, US",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4577-0599-1",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9681"
}
Back to top