Result Details
Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration
Straka Martin, Ing., Ph.D., FIT (FIT), DIFS (FIT), DCGM (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.
FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller
In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.
@inproceedings{BUT91473,
author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration",
booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
year="2012",
pages="1--4",
publisher="Politecnico di Milano",
address="Annecy"
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