Result Details

Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

KAŠTIL, J.; STRAKA, M.; KOTÁSEK, Z. Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration. The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012. p. 1-4.
Type
conference paper
Language
English
Authors
Kaštil Jan, Ing., Ph.D., DCSY (FIT)
Straka Martin, Ing., Ph.D., DIFS (FIT), DCGM (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Keywords

FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller

Annotation

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Published
2012
Pages
1–4
Proceedings
The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)
Publisher
Politecnico di Milano
Place
Annecy
BibTeX
@inproceedings{BUT91473,
  author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration",
  booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
  year="2012",
  pages="1--4",
  publisher="Politecnico di Milano",
  address="Annecy"
}
Projects
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
National Support for Project Reduced Certification Costs Using Trusted Multi-core Platforms, MŠMT, Společné technologické iniciativy, 7H10013, start: 2010-04-01, end: 2013-03-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Departments
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