Result Details

On Lookup Table Cascade-Based Realizations of Arbiters

MIKUŠEK, P.; DVOŘÁK, V. On Lookup Table Cascade-Based Realizations of Arbiters. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008. p. 795-802. ISBN: 978-0-7695-3277-6.
Type
conference paper
Language
English
Authors
Mikušek Petr, Ing.
Dvořák Václav, prof. Ing., DrSc., DCSY (FIT)
Abstract

This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.

Keywords

LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits

Published
2008
Pages
795–802
Proceedings
11th EUROMICRO Conference on Digital System Design DSD 2008
Conference
11th EUROMICRO Conference on Digital Systems Design 2008
ISBN
978-0-7695-3277-6
Publisher
IEEE Computer Society
Place
Parma
BibTeX
@inproceedings{BUT32056,
  author="Petr {Mikušek} and Václav {Dvořák}",
  title="On Lookup Table Cascade-Based Realizations of Arbiters",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  year="2008",
  pages="795--802",
  publisher="IEEE Computer Society",
  address="Parma",
  isbn="978-0-7695-3277-6",
  url="https://www.fit.vut.cz/research/publication/8635/"
}
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Design and hardware implementation of a patent-invention machine, GACR, Standardní projekty, GA102/07/0850, start: 2007-01-01, end: 2009-12-31, completed
Safety and security of networked embedded system applications, GACR, Standardní projekty, GA102/08/1429, start: 2008-01-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
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