Result Details
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
Kaštil Jan, Ing., Ph.D., DIFS (FIT), DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.
fault tolerant systems, reconfiguration, controller, FPGA, architecture
In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.
@inproceedings{BUT34654,
author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration",
booktitle="13th EUROMICRO Conference on Digital System Design, DSD'2010",
year="2010",
pages="365--372",
publisher="IEEE Computer Society",
address="Lille",
isbn="978-0-7695-4171-6"
}Secured, reliable and adaptive computer systems, BUT, Vnitřní projekty VUT, FIT-S-10-1, start: 2010-03-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed