Result Details

Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems

STRNADEL, J. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: Technical University Wien, 2011. p. 29-32.
Type
conference paper
Language
English
Authors
Strnadel Josef, Ing., Ph.D., DCSY (FIT)
Abstract

In the paper, a concept and an early analysis of an HW/SW architecture designed to prevent the SW from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual SW load being monitored with no intrusion to the SW. According to the actual SW load it is able to buffer all interrupts and related data while the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded.

Keywords

real time, interrupt, overload, prevention

URL
Published
2011
Pages
29–32
Proceedings
Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium
Conference
The 32nd IEEE Real-Time Systems Symposium
Publisher
Technical University Wien
Place
Vienna
BibTeX 
@inproceedings{BUT76464,
  author="Josef {Strnadel}",
  title="Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems",
  booktitle="Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium",
  year="2011",
  pages="29--32",
  publisher="Technical University Wien",
  address="Vienna",
  url="https://www.fit.vut.cz/research/publication/9776/"
}
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
National Support for Project Reduced Certification Costs Using Trusted Multi-core Platforms, MŠMT, Společné technologické iniciativy, 7H10013, start: 2010-04-01, end: 2013-03-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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